Computer memories typically can be divided into two main categories: volatile and nonvolatile. Volatile memories retain their data only so long as power is applied. Nonvolatile memories retain their data after power is removed.
One type of prior nonvolatile semiconductor memory is the flash electrically erasable programmable read-only memory ("flash EEPROM"). A flash EEPROM is typically comprised of banks of memory cells. The memory cells can be programmed by a user to store data in the form of digital bits (i.e., 0s and 1s), wherein an individual memory cell stores one bit of data.
Once programmed, the flash EEPROM retains its data until erased. After erasure, the flash EEPROM can be reprogrammed with new data. The same flash EEPROM is typically capable of being cycled (i.e., erased and reprogrammed) thousands of times.
A memory cell is typically erased by applying 12 volts to the source of the transistor comprising the memory cell while simultaneously grounding its floating gate. Upon completion of the erasure operation, an erase verication operation is performed to verify that all memory cells have been properly erased. During the erase verification procedure, the source needs to be grounded. A separate switching transistor is often used to effectively ground the source for performing an erase verification.
Serious complications can arise, however, because of the parasitic capacitance typically inherent in a memory cell. One problem is that when a cell is being erased, the parasitic capacitance is charged with 12 volts. Later, when the source is grounded, the 12 volts stored in the parasitic capacitance is discharged through the switching transistor. Given a large number of memory cells that need to be verified, the cumulative effect of each of the parasitic capacitances typically results in a relatively large amount of current (i.e., a current spike) being discharged through the switching transistor. Putting this amount of current through the switching transistor can cause it to break down and "snap back." The snap back condition typically dumps a large charge into the transistor's substrate, which can cause peripheral circuits to latch-up.
Another concern is that the metal line grounding the source of the switching transistor typically has parasitic resistance. Because the metal line is required to sink a large amount of current, the parasitic resistance typically tends to pull the source node high. As described above, the source node should be set at zero volts for erase verification.
Yet another disadvantage with typical prior art flash EEPROM layouts is that the drain of the switching transistor is placed nearest to the memory cell array. Typically, a flash array ring is interposed between the memory cell array and the switching transistor to isolate the memory cell array. Because the flash array ring is typically comprised of an N.sup.++ doped region and the switching transistor's drain is comprised of an N.sup.+ doped region, standard design rules specify that these two regions should be separated by a relatively large P doped area, such as the P-substrate. A large gap between these two regions contributes to increasing the overall die size of the flash EEPROM. A large die size is undesirable because fewer dies can be made from a given silicon wafer. This directly translates into higher production costs for manufacturing each flash EEPROM.